Packaging structure and method of a photosensitive module

ABSTRACT

A semiconductor die includes a semiconductor device fabricated in a substrate. The substrate has a front side, a back side, and an inclined sidewall extending from the back side to the front side. A contact pad is connected to the semiconductor device. The contact pad is embedded in an inter dielectric layer (IDL) disposed in the front side. The contact pad has a contact pad edge with a surface aligned along the inclined sidewall. A redistribution layer (RDL) is disposed on the inclined sidewall. The RDL is physically and electrically connected to the contact pad directly through the surface of the contact pad edge aligned along the inclined sidewall.

RELATED APPLICATION

This application claims priority to U.S. Provisional No. 63/368,745 filed on Jul. 18, 2023 and claims priority to U.S. Provisional No. 63/368,832 filed on Jul. 19, 2023, both of which are incorporated by reference in their entireties herein.

This application is also related to commonly assigned U.S. patent application Ser. No. 18/350,445, titled “THROUGH-SUBSTRATE-VIA IN PHOTOSENSITIVE MODULE,” filed on Jul. 11, 2023 and bearing Docket No. ONS04438US, which is incorporated by reference in its entirety herein.

FIELD

This description relates to a semiconductor device module that includes an optical sensor.

BACKGROUND

Digital optical sensors (e.g., a complementary metal-oxide-semiconductor image sensor (CIS) or a charge-coupled device (CCD)) are typically packaged in an integrated circuit (IC) package (i.e., a ceramic ball grid array package (CBGA) or a plastic ball grid array (PBGA) package along with a cover glass or lid placed over the optical sensor die.

SUMMARY

In a general aspect, a semiconductor die includes a semiconductor device fabricated in a substrate. The substrate has a front side, a back side, and an inclined sidewall extending from the back side to the front side. A contact pad is connected to the semiconductor device. The contact pad is embedded in an inter dielectric layer (IDL) disposed in the front side of the substrate. The contact pad has a contact pad edge with a surface aligned along the inclined sidewall of the substrate. A redistribution layer (RDL) is disposed on the inclined sidewall of the substrate. The RDL is physically and electrically connected to the contact pad directly through the surface of the contact pad edge aligned along the inclined sidewall of the substrate.

In a general aspect, a package includes an optical sensor die. The optical sensor die has an optically active surface area disposed on a front side of a substrate. A cover glass is attached to the front side of the substrate over the optically active surface area disposed on the front side of substrate. A conductive contact pad is embedded in an inter dielectric layer (IDL) disposed on the front side of the substrate. The substrate has an inclined sidewall extending from a back side of the substrate along an edge of the IDL to the front side of the substrate. The conductive contact pad has a contact pad edge defining a portion of the inclined sidewall.

In a further aspect, a redistribution layer (RDL) is disposed on the inclined sidewall. The RDL is physically and electrically connected to the conductive contact pad directly through the contact pad edge defining a portion of the inclined sidewall.

In a general aspect, a method includes preparing an assembly of a semiconductor substrate and a cover glass. The semiconductor substrate has an inter dielectric layer (IDL) disposed on a front side thereof. The IDL includes a contact pad. The cover glass is bonded to the front side of the semiconductor substrate by a layer of dam material.

The method further includes etching a trench from a back side of the semiconductor substrate through a semiconductor material of the semiconductor substrate up to the inter dielectric layer (IDL) disposed on the front side of the semiconductor substrate. The trench has a V-shape with inclined sidewalls and has a bottom at the contact pad included in the IDL.

The method further includes depositing an insulating dielectric layer by chemical vapor deposition on exposed surfaces of the semiconductor substrate including the inclined sidewalls of the trench and the back side of the semiconductor substrate, and depositing a compliant solder mask (CSM) layer on the insulating dielectric layer.

The method further includes forming (e.g., cutting) a notch through the bottom of the trench to extend the trench through the contact pad. The notch divides the contact pad into a first contact pad portion and a second contact pad portion with respective contact pad edges aligned with the inclined sidewalls of the trench. The method further includes disposing conductive material in the trench to connect the respective contact pad edges aligned with the inclined sidewalls of the trench to traces or contact pads in a redistribution layer (RDL) disposed on the back side of the semiconductor substrate.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates, in a cross-sectional view, portions of two photosensitive module packages that include optical sensor dies in which electrical connection to a front side of a die is made through a side-T type electrical connection directly through an edge of a contact pad exposed on an inclined sidewall of die, according to an implementation of the present disclosure.

FIG. 2 is a flow chart illustrating some example steps of an example process for fabricating a photosensitive module package, according to an implementation of the present disclosure.

FIGS. 3A through 3I illustrate cross-sectional views of portions of two photosensitive modules at different stages of construction.

FIG. 4 illustrates an example method for making an electrical connection between a front side of the semiconductor substrate and the back side of the semiconductor substrate in a photosensitive module or package.

Aspects of the present disclosure are best understood from the following detailed description when read with reference to the accompanying drawings. It is noted that, in accordance with common practice in the industry, various features are not necessarily drawn to scale. The relative dimensions of the various features may be increased or decreased for clarity or ease in visualization. In the drawings, like reference symbols may indicate like and/or similar components (elements, structures, etc.) in different views. The drawings illustrate generally, by way of example, but not by way of limitation, various implementations discussed in the present disclosure. Reference symbols shown in one drawing may not be repeated for the same, and/or similar, elements in related views. Reference symbols that are repeated in multiple drawings may not be specifically discussed with respect to each of those drawings but are provided for context between related views. Also, not all like elements in the drawings are specifically referenced with a reference symbol when multiple instances of an element are illustrated.

DETAILED DESCRIPTION

An optical sensor (e.g., a complementary metal-oxide semiconductor (CMOS) pixel sensor) fabricated on a semiconductor device die (semiconductor die) (e.g., optical sensor die) includes an optically active surface area (OASA) with an array of pixel sensors (e.g., a x-y array of pixels) responsible for converting a light and color spectrum into electrical signals. Each pixel sensor in the array of pixels may, for example, include a photo diode or a photo transistor that senses and converts incident light into an electrical signal. The OASA of an optical sensor may also include, for example, a micro lens array (e.g., a x-y array of micro lenses) to help funnel incoming light into each pixel (thereby increasing the sensitivity of the optical sensor) and or include a color filter array (CFA) (e.g., a x-y array of filters) (i.e., a mosaic of tiny color filters coupled to the pixel sensors to capture color information).

An optically transparent cover (also can be referred to as a cover glass or lid) overlays the optical sensor die in many optical sensor package configurations. The cover glass may be attached to the semiconductor die, for example, by a bead of adhesive material (e.g., an epoxy or a resin) disposed on edges of the semiconductor die. The cover glass provides a hard cleanable surface as the top surface of the sensor the optical sensor die and can physically shield the delicate optical sensor surface (e.g., the optically active surface area) from physical damage (caused, e.g., by dirt, dust, fingerprints, grease, smudges, etc.). The cover glass itself can provide a hard cleanable surface as the top surface of the packaged optical sensor die.

In example implementations, the cover glass is positioned above the optical sensor surface with a gap (e.g., an air gap or other transparent material-filled gap) interposed between a bottom surface of the cover glass and the optically active surface area (OASA) (i.e., the area above the sensor pixels, and including the CFA and micro lens layers). A dam material (e.g., an epoxy or resin) may hold the cover glass in place above the optical sensor surface.

This disclosure describes packaging of individual optical sensor dies in individual chip-scale packages (CSPs) (i.e., individual photosensitive modules), and methods for batch fabrication of the individual photosensitive modules using wafer-level processing steps. After completion of the wafer-level processing steps, the wafer on which the individual image sensor dies are fabricated may be singulated (scribed, sawn, or diced) to separate the individual chip-scale packages (CSPs).

The side of the optical sensor die on which the OASA is disposed (and over which the cover glass is placed) may be referred to as the front side (or front portion) of the optical sensor die, and the opposite side (opposite the side with the OASA or the cover glass) may be referred to as the back side (or back portion) of the optical sensor die. The front portion and the back portion of the optical sensor die may include generally planar surfaces in an x-y plane (e.g., front surface FS, back surface BS). The optical sensor die may have a vertical thickness or height H in the z direction between the front side and the back side of the optical sensor die. A sidewall (e.g., a sloping sidewall) of the optical sensor die may extend from the back portion to the front portion of the optical sensor die. The front portion of the optical sensor die may include contact pads (e.g., conductive contact pads) that provide electrical connection to devices and circuits that may be built in the front portion of the die.

In example implementations, the semiconductor material in an optical sensor die fabricated in a semiconductor substrate may be in a form of a slab with a trapezoidal shape in cross section. The trapezoidal shape of the semiconductor material can include a pair of substantially parallel sides (bases, formed by the front side and the back side surfaces) and a pair of non-parallel sides (legs, formed by a pair of the sloping sidewalls). The legs or sloping sidewalls of the optical sensor die may correspond to a sidewall of a through substrate via (TSV) that may be etched along scribe lines in the substrate in the process of singulating and separating individual optical sensor die (a photosensitive module.)

A diameter (or width) of an opening of the TSV adjacent to the back surface BS of optical sensor die can be generally greater than the diameter (or width) of an opening of the TSV adjacent to the front surface FS of the optical sensor die. As a result, the TSV can have inclined sidewalls (in other words, the legs of the trapezoidal shape of the semiconductor material in the optical sensor die) that are generally sloping inward from the opening of the TSV adjacent to the back surface BS of optical sensor die toward a bottom of the TSV adjacent to the front surface FS of optical sensor die.

A passivation layer (e.g., silicon oxide silicon nitride, or other dielectric) may be disposed on the back surface (BS) of an optical sensor die in a photosensitive module. Further, a redistribution layer (RDL) (e.g., a signal redistribution layer) may be disposed on or in the passivation layer on the back surface (BS) of the optical sensor die. The RDL may be made of insulating material, for example, a dam material (e.g., an epoxy or resin) and may, for example, include conductive traces or pads (e.g., metal contact pads) of a back side metallization layer of the optical sensor die. The RDL may, for example, include solder balls of ball grid array (BGA) disposed on the back side for back side contact to a package (module) of the optical sensor die.

A through-substrate-via (TSV) may be etched (e.g., vertically) through an optical sensor die to provide access for electrical connections between the back side (e.g., the back portion) of the die and the front side (e.g., front portion) of optical sensor die. The TSV may, for example, provide a physical access path for an electrical connection to a contact pad (disposed, e.g., next to the OASA) on the front side (e.g., front surface FS) of the optical sensor die from the back side (e.g., back surface BS) of the die. The electrical connection may, for example, include a conductive material trace or a lead line formed on sidewalls of the TSV.

A conductive material (e.g., a metal such as nickel (Ni)) may be patterned in the TSV (e.g., disposed on sides of the TSV) to form a redistribution layer RDL, which can provide electrical connections to the front side (e.g., front portion) of optical sensor die from the back side (e.g., back portion) of optical sensor die. The conductive material (e.g., metal) disposed on sidewalls of the TSV may connect, for example, a contact pad at the front side (e.g., at about the front surface FS) of optical sensor die to the traces or contact pads in the RDL disposed on the back side (e.g., at about the bottom surface BS) of optical sensor die.

The patterned conductive material disposed in the TSV for the electrical connections may include aluminum, copper, gold, platinum, nickel, tin, a combination thereof, a conductive polymer material, a conductive ceramic material (such as indium tin oxide or indium zinc oxide), or another suitable conductive material. The conductive material may be disposed on sidewalls of the TSV, for example, by a metal deposition process (e.g., sputtering, chemical vapor deposition (CVD), or metal plating process, etc.)

In example implementations, the TSV may cut through a contact pad on the front side such that a side edge (cross section) of the contact pad is exposed on an inclined sidewall of the optical sensor die. In other words, the contact pad has an edge with a surface of the edge aligned along the inclined sidewall. The electrical connections to the front side (e.g., front surface FS) of the optical sensor die from the back side (e.g., back surface BS) of optical sensor die may include a side-trench (side-T) type of connection. In the side-T type connection, an electrical connection from the back side to the front side of the optical sensor die is made by a trace or lead line deposited on the sidewall (inclined sidewall) of the TSV directly contacting the exposed side (cross section) of the contact pad on the sidewall of the TSV.

In example implementations, the contact pad may have a plate-like shape (e.g., in an x-y plane) with a length extending, for example, in an x direction (e.g., direction xx-xx, as shown in FIG. 1 ). In example implementations, the inclined sidewall while generally extending in the z direction between the front side and the back side of the optical sensor die is non-orthogonal to the contact pad. As shown in FIG. 1 , the inclined sidewall may extend in a direction ss-ss in the x-z plane.

In accordance with the principles of the present disclosure, an inclined sidewall of a semiconductor material slab in an optical sensor die has a chamfered shape adjacent to the contact pad on the front side of the optical sensor die. The chamfered structure (e.g., the step-like structure) may be formed by depositing a layer of an insulating dielectric material in the TSV. The layer of an insulating dielectric material may be deposited using a chemical vapor deposition (CVD) techniques. The chamfered shape may include a flat surface adjacent to the contact pad between two sections of the inclined sidewall. In other words, the inclined sidewall may have a step-like structure with a step over the contact pad on the front side of the optical sensor die.

RDL traces and lead lines may be deposited on the inclined sidewalls of the TSV to form a side-T type electrical connection directly through an exposed side (edge) of the contact pad on a section of the inclined sidewall of the TSV. The exposed side (edge) of the contact pad may have a surface that is aligned with or along the inclined sidewall. In other words, the contact pad may have a contact pad edge defining a portion of the inclined sidewall of the TSV.

A proximity of the trace or lead line deposited on the sidewall of the TSV to the semiconductor material in the optical sensor die can result in leakage problems. The step-like structure (e.g., the chamfered structure) with a step over the contact pad on the front side of the optical sensor die may increase the separation between conductive RDL traces and lead lines deposited on the sidewalls of the TSV and the semiconductor material of the optical sensor die. This increased separation (e.g., corresponding to a width W of the step) can reduce leakage of current from the conductive RDL traces and lead lines deposited on the sidewalls of the TSV to the semiconductor material.

FIG. 1 schematically shows, in a cross sectional view, portions of two photosensitive modules (e.g., a right portion of photosensitive module package 100-1, a left portion of photosensitive module package 100-2) that include optical sensor dies (e.g., optical sensor dies 120-1, 120-2). In the photosensitive modules, electrical connection to a contact pad (e.g., contact pad 102) on the front side of a die is made through a side-T type electrical connection directly through an exposed side (edge) of the contact pad on an inclined sidewall of die.

The two photosensitive modules (e.g., photosensitive module package 100-1, 100-2) may be fabricated in, and singulated from, an assembly (e.g., assembly 300, FIG. 3A) of a semiconductor device substrate (e.g., semiconductor substrate 310, FIG. 3A) and a cover glass (e.g., cover glass 108),

FIG. 1 schematically shows the two photosensitive modules (e.g., photosensitive module package 100-1, 100-2) as being physically separated and displaced from each other (e.g., in an x direction) after singulation of assembly 300 along a scribe line SL (FIG. 3I).

The optical sensor dies may be formed in a semiconductor substrate (e.g., semiconductor substrate 310, FIG. 3A). The optical sensor dies (e.g., optical sensor dies 120-1, 120-2) may include a front side (front surface FS) and a back side (back surface BS), and may include an optically active sensor area (OASA) (e.g., OASA 101) formed on the front side of the substrate. For visual clarity and in consideration the size and scale of the figure for fitting on the page, FIG. 1 shows only the OASA (e.g., OASA 101) disposed on the front side of the portion of optical sensor die 120-2. The left portion of optical sensor die 120-1 including the OASA on its front side is off scale and not shown in the page of FIG. 1 .

In example implementations, cover glass 108 may be placed over the semiconductor substrate and attached to the front surfaces of the optical sensor dies (e.g., optical sensor dies 120-1, 120-2) by a layer (e.g., dam 106) of dam material (e.g., an epoxy, a solder mask material, etc.)

In example implementations, an inter dielectric layer (IDL) (e.g., IDL layer 104) may be disposed on or included in the front side of the optical sensor dies (e.g., optical sensor dies 120-1, 120-2). IDL layer 104 may include the contact pads (e.g., contact pad 102) for electrical connection to the devices and circuits (not shown) in the dies. Contact pad 102, which may be made of a metal or other conductive material, may provide electrical connection to devices and circuits (not shown) that may be built in the front portion of the optical sensor dies.

As shown in FIG. 1 , the optical sensor dies may have inclined sides (e.g., inclined sidewall 130) between the back surface (BS) and the front surface (FS) of the optical sensor dies. The inclined sides (e.g., inclined sidewall 130) may correspond to the sides of a TSV (e.g., TSV 180) etched through the substrate in a process for singulating or dicing individual optical sensor die. TSV 180 may extend through the semiconductor material of the substrate and the IDL layer (e.g., IDL layer 104) to a TSV bottom (e.g., TSV bottom 180B) beyond the IDL layer (e.g., as shown in FIG. 1 , below the IDL layer). In example implementations, TSV 180 may extend, for example, into the dam material (e.g., dam 106) below the IDL layer. In example implementations, TSV 180 may extend, only part way into the dam material (e.g., dam 106) to reach the TSV bottom (e.g., TSV bottom 180B) at a depth d in the dam material below the IDL layer 104.

An inclined sidewall 130 of the optical sensor dies may include a flat step section (e.g., step section 130-3) of width W extending horizontally (e.g., in the x direction) between two inclined sections (e.g., inclined sections 130-1, 130-2) of inclined sidewall 130 of the optical sensor dies. Section 130-3 may lie above the contact pad (e.g., contact pad 102) embedded in IDL layer 104 on the front surface FS of the optical sensor dies. Inclined section 130-1 may extend from the back surface BS to an edge (e.g., an inside edge E1) of step section 130-3 above the contact pad (e.g., contact pad 102). Inclined section 130-2 may extend from an edge (e.g., an outside edge E2) of step section 130-3 above the contact pad (e.g., contact pad 102) to a position below the IDL layer 104 on the front side (FS) of the optical sensor die (e.g., to a TSV bottom 180B below the IDL layer 104).

In other words, inclined section 130-1 is retracted or offset (e.g., in the x direction) from inclined section 130-2 by a distance corresponding to the width W of the step section 130-3.

Inclined section 130-2 may cut through the IDL layer 104 such that an edge (edge SC) of the contact pad (e.g., contact pad 102) is exposed on inclined section 130-2 of the TSV sidewall. In other words, the contact pad may have a contact pad edge that defines a portion of the inclined section 130-2 of the TSV sidewall. Electrical connection to the contact pad can be made by RDL elements (e.g., RDL 150) deposited on inclined section 130-2 directly through the edge (edge SC) of the contact pad (e.g., contact pad 102) that is exposed on inclined section 130-2. RDL 150 may conform with the shape (slope) of inclined section 130-2 and directly cover the surface of the edge (edge SC) of the contact pad (e.g., contact pad 102) that is exposed on inclined section 130-2. As shown in FIG. 1 , RDL 150 deposited on inclined section 130-2 may extend in direction ss-ss in the x-z plane. Direction ss-ss of RDL 150 deposited on inclined section 130-2 is non-orthogonal and non-parallel to direction xx-xx of the contact pad 102. RDL 150 does not intersect the contact pad but lies over inclined section 130-2 to cover the surface of the edge (edge SC) of the contact pad (e.g., contact pad 102) that is exposed on inclined section 130-2. In other words, the materials of RDL 150 may be in direct physical and electrical contact with the exposed edge SC of the contact pad. Before formation of RDL 150, an insulating layer (e.g., layer 140) may be deposited on portions of inclined sidewall 130 (e.g., on inclined section 130-1, and step section 130-3) to isolate the semiconductor materials (e.g., semiconductor material 120S) of the body of the optical sensor dies from RDL 150

In example implementations, layer 140 (e.g., a compliant or conformal solder mask (CSM)) may be deposited the back surface and portions of the inclined sidewalls (e.g., inclined section 130-1 and step section 130-3) of the optical sensor dies. In example implementation, RDL 150 deposited on layer 140 may include a conductive material (e.g., metal layer 152) and or a lead line (e.g., lead line 154). Solder balls (e.g., solder ball 192) may be deposited on contact pads (not shown) connected to RDL 150 on the back side of the optical sensor dies to provide an external ball grid array (BGA) back side contact for the two photosensitive modules (e.g., photosensitive module package 100-1, 100-2). Electrical connection from the back side to the front side of the optical sensor dies is made through the BGA and the side-T connection to the edge (edge SC) of the contact pad (e.g., contact pad 102) exposed on inclined section 130-2 on the front side.

In example implementations, the optical sensor dies in the photosensitive modules (e.g., photosensitive module package 100-1, 100-2) may be at least partially encapsulated in a molding material 190.

FIG. 2 is a flow chart illustrating some example steps of an example process 200 for fabricating a photosensitive module. Process 200 may include steps for making electrical connections between a front side and a back side of an optical sensor die in the photosensitive module (optical sensor package) through edges of contact pads that are exposed on inclined sides of the optical sensor die. The electrical connections may be made using a stepped-bottom TSV (e.g., TSV 180) that may be used to singulate (in other words, separate) individual optical sensor die fabricated in a semiconductor substrate. The electrical connections may be made using a side-T type of physical connection to edges of contact pads that are exposed on inclined sides of the stepped-bottom TSV. The TSV may be aligned with scribe lines along which the semiconductor substrate can be sawn or diced to form the individual optical sensor die.

In process 200, a step 201: Solder mask dam glass (SMDG), may include disposing dam material (e.g., an epoxy, or other adhesive material) on a cover glass, and a step 202: Wafer to Glass Bonding, may include placing the cover glass above an OASA on a semiconductor substrate and bonding the cover glass to the semiconductor substrate using the dam material. Further, in process 200, a step 203: Grind silicon (GS), may include back side thinning (e.g., back side grinding or etching) of the semiconductor substrate (e.g., a silicon substrate) to a target thickness (e.g., a thickness of about 75 μm to 200 μm) (e.g., 175 μm).

Next in process 200, a step 204: Etch 1, may include etching the thinned back side of the semiconductor substrate to reduce grinding-induced stress in the semiconductor substrate.

Next, a step 205: lithographic etching (LE), may include patterning and etching a photoresist layer (e.g., a solder mask layer) to define an opening width for a TSV, followed by a step 206: Etch 2, which may include etching the semiconductor substrate (e.g., silicon) to form the TSV extending from the back side of the semiconductor substrate up to IDL layers on the front side of the semiconductor substrate. The IDL layers on the front side may include the contact pads for electrical connections to the devices and circuits built in, or on, the front side of the semiconductor substrate.

In example implementations, the opening in photoresist layer (e.g., a solder mask layer) on the back surface of the semiconductor substrate may be aligned with die perimeter lines (e.g., scribe lines) that can be used for singulating or dicing individual optical sensor die from the semiconductor substrate into individual photosensitive modules (e.g., at the end of process 200). The opening in photoresist layer on the back surface of the semiconductor substrate may be also aligned with a contact pad included in the IDL layers on the front side of the semiconductor substrate.

In process 200, step 206: Etch 2, may include etching trenches (TSVs) in the semiconductor substrate through the openings in the solder mask layer on the back surface of the semiconductor substrate. At step 206, the etching of the trench may be carried out using one or more etchants (dry etchants) to etch through the silicon material and to remove the remaining solder mask material. The etchants may etch through the silicon material of the substrate and stop at the dielectric materials of IDL layers on the front side of the semiconductor substrate. Internal sidewalls (inclined sidewalls) of the trench may extend from a top portion of the trench up to the IDL layers.

A trench formed at this step 206 may extend vertically from the back surface of semiconductor substrate up to the first of the IDLs disposed on the front surface of the semiconductor substrate. The first IDL may cover the metal contact pad included in the second IDL disposed on the front surface of the semiconductor substrate. The trench (e.g., TSV 180) formed through an opening aligned with the metal contact pad may have a narrower bottom opening at the first IDL.

In accordance with the principles of the present disclosure, process 200 may further include a step 207: Chemical Vapor Deposition (CVD), followed by a step 208: conformal solder mask (CSM), and a step 209: Notch (NTH).

Step 207: Chemical Vapor Deposition (CVD), may involve depositing a layer of insulating material on the back side of the substrate and on sidewalls of trench. Step 208: compliant solder mask (CSM), may involve disposing a solder mask layer on the back side of the substrate and on sidewalls of trench, to define an opening through the trench bottom aligned with a scribe line for separation (singulation) of the individual image sensor dies.

Step 209: Notch (NTH) may include forming (e.g., making) a cut (e.g., a notch or cut) to extend the bottom of the trench through the IDL layers at the bottom of the trench formed at step 206 and scribe the cover glass bonded to the semiconductor substrate. This notch or cut may be made, for example, by a mechanical saw or a laser saw. The notch or cut may extend through the metal contact pad included in the IDL layers disposed on the front surface of the semiconductor substrate. In other words, the metal contact pad may be cut into two portions. The edges of these two metal contact pad portions may be exposed on the sidewalls of the trench.

Further, process 200 may include steps for forming an RDL structure connecting the back side to the front side. These steps may include step 210: sputtering conductive lead material (SPL), which may include sputtering conductive materials (e.g., aluminum, copper, nickel, etc.) for forming lead lines on the sidewalls of the TSV and on the back side of the substrate; step 211: lead line (LL), which may include lithographically defining a lead line; and step 212: metal deposition (MD), which may include metal deposition (e.g., copper, aluminum, nickel, etc.) or other conductive materials to form traces and lead lines of the RDL structure.

Process 200 for fabricating the photosensitive module may further include additional wafer level processing steps for developing the redistribution layer on the back side of the semiconductor substrate before dicing or singulation of the semiconductor substrate into individual photosensitive modules. These additional wafer-level processing steps may, for example, include step 213: solder mask formation (SMF), which may involve depositing a passivating solder mask layer on the back side of the substrate, and patterning the solder mask layer to define conductive pads for positioning solder balls of a ball grid array (BGA). A next step 214: Ball Grid Array (BGA), may include placing solder balls on the designated conductive pads on the back side of the substrate.

In process 200, a further step 215: Dicing, may include dicing or singulation of the semiconductor substrate and the attached cover glass along the scribe lines into individual photosensitive modules.

FIGS. 3A through 3I illustrate cross-sectional views of a photosensitive module at different stages of construction.

FIG. 3A shows, for example, an assembly 300 of a cover glass 108 and a semiconductor substrate 310 at an initial stage of construction (e.g., after step 202 in process 200). In assembly 300, semiconductor substrate 310 may, for example, be a semiconductor wafer (e.g., a 200 mm diameter silicon wafer). Semiconductor devices 160 (e.g., an optical sensor device) may be fabricated in or on the substrate (e.g., about a front side FS of the substrate). Semiconductor substrate 310 may include material for several semiconductor die (e.g., semiconductor die 120-1, 120-2, FIG. 1 ) that can be individually singulated (or diced) from the substrate, for example, along die perimeter lines (e.g., scribe lines 12S). In example implementations, the semiconductor die may be an optical sensor die that includes an optically active surface area (OASA) (e.g., OASA 101). The OASA may be formed on the front side (front surface) of the semiconductor substrate.

In assembly 300, cover glass 108 may be disposed above OASA 101 and attached (bonded) to semiconductor substrate 310 by a layer of dam material (e.g., dam 106). In example implementations, cover glass 108 may have a thickness T in a range of about 200 μm to 900 μm (e.g., 400 μm).

In example implementations, semiconductor substrate 310 may be thinned (e.g., by back side griding or etching at step 203 of process 200). FIG. 3B shows, for example, assembly 300 with substrate 310 thinned (e.g., by back side griding or etching) to a thickness t in a range of about 50 μm to 150 μm (e.g., 85 μm).

As shown in FIG. 3A and FIG. 3B, a passivating dielectric layer (e.g., inter dielectric layer (IDL) 104) also may be disposed on the front surface of the semiconductor substrate. IDL layer 104 may have a thickness in a range of about 0.4 μm to 2 μm (e.g., 0.6 μm). The IDL layer, in addition to passivating exposed silicon and metal surfaces, may include conductive elements (e.g., contact pad 102) of a redistribution layer disposed on the front side of the semiconductor die for conveying electrical signals to and from semiconductor devices 160 in the semiconductor die (e.g., semiconductor die 120-1, 120-2). In example implementations, contact pad 102 may be made of metal (e.g., aluminum, copper, etc.) or other conductive material.

FIG. 3C shows, for example, assembly 300 after a next stage of construction (e.g., after step 204, step 205, and step 206 of process 200) with a through substrate via (e.g., TSV 180) etched through the semiconductor substrate from the back side (e.g., back side BS) to access the contact pad (e.g., contact pad 102) disposed on the front side FS of the semiconductor substrate. TSV 180 may be aligned with the die perimeter lines (e.g., scribe line 12S) that can be used for singulating or dicing individual semiconductor die (e.g., semiconductor die 120-1, 120-2) from assembly 300. In example implementations, TSV 180 may be shaped as a V-shape cut with an opening at the back side that is larger than an opening of the TSV at the front side FS of the semiconductor substrate. TSV 180 may be aligned with scribe line 12S, which may intersect (e.g., bisect) contact pad 102.

FIG. 3D shows, for example, assembly 300 after a next stage of construction (e.g., after step 207 and step 208 of process 200) with a passivating layer (e.g., layer 170) is deposited on the back side of the assembly and on the sidewalls of TSV 180. In example implementations, layer 170 may include a compliant solder mask (CSM) material.

FIG. 3E shows, for example, assembly 300 after a next stage of construction (e.g., after step 209, process 200) with a notch cut so that the TSV 180 extends through contact pad 102 into the dam material (e.g., dam 106) to reach a TSV bottom (e.g., TSV bottom 180B) at a depth d in the dam material (FIG. 1 ). The notch cut, which may be a saw cut or a laser cut, can divide the contact pad into two portions (e.g., contact pad 102-1 and contact pad 102-2) corresponding, for example, to semiconductor die 120-1 and semiconductor die 120-2. Edges (e.g., edge E) of the two portions (e.g., contact pad 102-1 and contact pad 102-2) may be exposed on the sidewalls of the TSVs.

FIG. 3F shows, for example, assembly 300 after a next stage of construction (e.g., after step 210, step 211, and step 212 in process 200) with traces and lead lines of an RDL structure (e.g., RDL 150, FIG. 1 ) connecting the exposed edges (edge E) of the contact pad portions (e.g., contact pad 102-1 and contact pad 102-1) on the front side to the back side of the semiconductor dies. The RDL structure (e.g., RDL 150) may be created by depositing layers of conductive materials (e.g., metals) on the sidewalls of TSV 180 (including the exposed edges (edge E) of the contact pads) and on the back side of assembly 300. These layers may be lithographically patterned and etched to define, for example, landing pads for solder balls of a ball grid array (BGA) for back side contact.

FIG. 3G shows, for example, assembly 300 after a next stage of construction (e.g., after step 213, process 200) in which a solder mask layer (e.g., solder mask layer 175) is deposited on RDL 150 on the back side of the assembly. The solder mask layer 175 is patterned with openings (e.g., opening 177) corresponding to designated locations on RDL 150 for placement of the solder balls of the BGA.

FIG. 3H shows, for example, assembly 300 after a next stage of construction (e.g., after step 214, process 200) in which solder balls (solder balls 192) of the BGA have been placed on RDL 150 at the designated locations (e.g., in openings 177 of layer 175).

FIG. 3I shows the assembly of FIG. 3G being schematically sawn along die perimeter lines (e.g., scribe lines 12S) to singulate the assembly into individual photosensitive modules (e.g., photosensitive module package 100-1, photosensitive module package 100-2). Package 100-1 and package 100-2 may include respective individual semiconductor dies (e.g., semiconductor die 120-1 and semiconductor die 120-2) with a cover glass 108.

FIG. 4 shows an example method 400 for making an electrical connection between a front side of the semiconductor substrate and the back side of the semiconductor substrate in an photosensitive module or package constructed using wafer-level processing steps.

Method 400 includes preparing an assembly of a semiconductor substrate and a cover glass (410). The cover glass may be bonded to the front side of the semiconductor substrate by a layer of dam material. The semiconductor substrate may include at least two optical sensor devices fabricated therein. The semiconductor substrate may further include an inter dielectric layer (IDL) disposed on a front side thereof. The IDL may include a contact pad disposed between the at least two optical sensor devices.

Method 400 further includes etching a trench from a back side of the semiconductor substrate through a semiconductor material of the semiconductor substrate up to the inter dielectric layer (IDL) disposed on a front side of the semiconductor substrate (420). The trench may have a V-shape with inclined sidewalls and have a bottom surface at the contact pad included in the IDL. Method 400 further includes depositing an insulating dielectric layer by chemical vapor deposition on exposed surfaces of the semiconductor substrate (430). The insulating dielectric layer may be deposited on exposed surfaces including the inclined sidewalls of the trench and the back side of the semiconductor substrate.

Method 400 further includes depositing compliant solder mask (CSM) layer on the insulating dielectric layer (440) and cutting a notch through the bottom of the trench to extend the trench through the contact pad (450). The notch may divide the contact pad into a first contact pad portion and a second contact pad portion with respective contact pad edges exposed on the inclined sidewalls of the trench.

Method 400 further includes disposing conductive material in the trench (460). The conductive material disposed in the trench may cover the respective contact pad edges exposed on the inclined sidewalls of the trench and connect the respective contact pad edges to traces or contact pads in a redistribution layer (RDL) disposed on the back side of the semiconductor substrate.

In example implementations, method 400 may further include disposing a solder mask layer on the RDL disposed on the back side of the semiconductor substrate and patterning the solder mask layer with at least one opening for placement of a solder ball of a ball grid array (BGA).

In example implementations, method 400 may further include encapsulating at least a portion the assembly in a molding material.

In example implementations, method 400 may further include singulating the assembly along the trench to isolate or separate an individual package.

In example implementations, the conductive material disposed in the trench 460 and the traces or contact pads of the redistribution layer (RDL) disposed on the back side of the semiconductor substrate may, for example, include at least one of nickel, aluminum, and copper.

It will be understood that, in the foregoing description, when an element, such as a layer, a region, or a substrate, is referred to as being on, connected to, electrically connected to, coupled to, or electrically coupled to another element, it may be directly on, connected or coupled to the other element, or one or more intervening elements may be present. In contrast, when an element is referred to as being directly on, directly connected to or directly coupled to another element or layer, there are no intervening elements or layers present. Although the terms directly on, directly connected to, or directly coupled to may not be used throughout the detailed description, elements that are shown as being directly on, directly connected or directly coupled can be referred to as such. The claims of the application may be amended to recite exemplary relationships described in the specification or shown in the figures.

As used in this specification, a singular form may, unless definitely indicating a particular case in terms of the context, include a plural form. Spatially relative terms (e.g., over, above, upper, under, beneath, below, lower, top, bottom, and so forth) are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. In some implementations, the relative terms above and below can, respectively, include vertically above and vertically below. In some implementations, the term adjacent can include laterally adjacent to or horizontally adjacent to.

Some implementations may be implemented using various semiconductor processing and/or packaging techniques. Some implementations may be implemented using various types of semiconductor device processing techniques associated with semiconductor substrates including, but not limited to, for example, silicon (Si), silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), and/or so forth.

While certain features of the described implementations have been illustrated as described herein, many modifications, substitutions, changes, and equivalents will now occur to those skilled in the art. For instance, features illustrated with respect to one implementation can, where appropriate, also be included in other implementations. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the scope of the implementations. It should be understood that they have been presented by way of example only, not limitation, and various changes in form and details may be made. Any portion of the apparatus and/or methods described herein may be combined in any combination, except mutually exclusive combinations. The implementations described herein can include various combinations and/or sub-combinations of the functions, components and/or features of the different implementations described. 

1. A semiconductor die, comprising: a substrate including a semiconductor device, the substrate having a front side, a back side, and an inclined sidewall extending from the back side to the front side; a contact pad connected to the semiconductor device, the contact pad embedded in an inter dielectric layer (IDL) disposed in the front side and the contact pad having a contact pad edge with a surface aligned along the inclined sidewall; and a redistribution layer (RDL) disposed on the inclined sidewall, the RDL being physically and electrically connected to the contact pad directly through the surface of the contact pad edge aligned along the inclined sidewall.
 2. The semiconductor die of claim 1, wherein the inclined sidewall includes a first inclined section extending from the back side toward the front side along a semiconductor material of the semiconductor die, a flat step section disposed above the contact pad embedded in the IDL disposed on the front side, and a second inclined section extending along an edge of the IDL disposed the front side.
 3. The semiconductor die of claim 2, further comprising an insulating layer disposed on the first inclined section and the flat step section of the inclined sidewall to isolate the semiconductor material of the semiconductor die from the RDL.
 4. The semiconductor die of claim 2, wherein the RDL includes conductive material forming conductive traces and lead lines connecting the back side of the semiconductor die to the front side of the semiconductor die.
 5. The semiconductor die of claim 2, wherein the RDL includes conductive traces and pads formed on the back side of the semiconductor die.
 6. The semiconductor die of claim 2, wherein the RDL includes solder balls disposed in a ball grid array (BGA).
 7. The semiconductor die of claim 2, wherein the RDL includes at least one of aluminum, copper, and nickel.
 8. The semiconductor die of claim 1, wherein the contact pad is a metal contact pad including at least one of aluminum and copper.
 9. The semiconductor die of claim 1, wherein the semiconductor device is an optical sensor device and the semiconductor die further comprises an optically active surface area (OASA) disposed on the front side of substrate.
 10. The semiconductor die of claim 9, further comprising: a cover glass attached to the front side of the semiconductor die over the optically active surface area disposed on the front side of substrate.
 11. A package, comprising: an optical sensor die including an optically active surface area disposed on a front side of a substrate; a cover glass attached to the front side of the substrate over the optically active surface area disposed on the front side of substrate; a conductive contact pad embedded in an inter dielectric layer (IDL) disposed on the front side of the substrate, the substrate having an inclined sidewall extending from a back side of the substrate along an edge of the IDL to the front side of the substrate, and the conductive contact pad having a contact pad edge defining a portion of the inclined sidewall; and a redistribution layer (RDL) disposed on the inclined sidewall, the RDL being physically and electrically connected to the conductive contact pad directly through the contact pad edge defining a portion of the inclined sidewall.
 12. The package of claim 11, wherein the inclined sidewall includes a first inclined section extending from the back side toward the front side of the optical sensor die up to the IDL, a flat step section disposed above the conductive contact pad embedded in the IDL disposed on the front side, and a second inclined section extending along the edge of the IDL disposed the front side, the second inclined section being offset from the first inclined section by a width of the flat step section in a direction along the conductive contact pad.
 13. The package of claim 12, further comprising an insulating layer disposed on the first inclined section and the flat step section of the inclined sidewall to isolate a semiconductor material of the optical sensor die from the RDL.
 14. The package of claim 13, wherein the RDL includes conductive material forming conductive traces and lead lines connecting the back side of the optical sensor die to the front side of the optical sensor die.
 15. The package of claim 13, wherein the RDL includes conductive pads formed on the back side of the optical sensor die for placement of solder balls of a ball grid array (BGA).
 16. The package of claim 15, further comprising solder balls of a ball grid array (BGA).
 17. A method comprising: preparing an assembly of a semiconductor substrate and a cover glass, the semiconductor substrate having an inter dielectric layer (IDL) disposed on a front side thereof, the IDL including a contact pad, the cover glass being bonded to the front side of the semiconductor substrate by a layer of dam material; etching a trench from a back side of the semiconductor substrate through a semiconductor material of the semiconductor substrate up to the inter dielectric layer (IDL) disposed on the front side of the semiconductor substrate, the trench having a V-shape with inclined sidewalls and having a bottom at the contact pad included in the IDL; depositing an insulating dielectric layer by chemical vapor deposition on exposed surfaces of the semiconductor substrate including the inclined sidewalls of the trench and the back side of the semiconductor substrate; depositing a compliant solder mask (CSM) layer on the insulating dielectric layer; forming a notch through the bottom of the trench to extend the trench through the contact pad, the notch dividing the contact pad into a first contact pad portion and a second contact pad portion with respective contact pad edges aligned with the inclined sidewalls of the trench; and disposing conductive material in the trench to connect the respective contact pad edges aligned with the inclined sidewalls of the trench to traces or contact pads in a redistribution layer (RDL) disposed on the back side of the semiconductor substrate.
 18. The method of claim 17, wherein the semiconductor substrate includes at least two optical sensor devices fabricated therein, and the contact pad included in the IDL is disposed between the at least two optical sensor devices.
 19. The method of claim 17, further comprising: disposing a solder mask layer on the RDL disposed on the back side of the semiconductor substrate and patterning the solder mask layer with at least one opening for placement of a solder ball of a ball grid array (BGA).
 20. The method of claim 19, further comprising encapsulating at least a portion the assembly in a molding material.
 21. The method of claim 19, further comprising singulating the assembly along the trench to isolate or separate an individual package. 